VLSI Design-EC6601 - FDTP - Anna University, MIT Campus

The Department of Electronics Engineering,Madras Institute of Technology Campus,Anna University, Chennai – 600044 has organized the FDTP " VLSI Design – EC6601"  on 20th November to 26th November 2017 .

Objective :

Fundamentals of VLSI design
MOS transistor principles
Stick and layout diagrams
Combinational circuits
Sequential circuits
Memory architectures
Arithmetic building blocks
ASIC design
FPGA routing procedures
Altera based system design

Who can attend ?

The Faculty Members from Engineering Colleges affiliated to Anna University are eligible to attend this program .

Registration Details :

Interested persons are requested to fill up the registration form in the prescribed format and send it to the Coordinator address given below by post /email  to reach by on or before 17th Nov. 2017 .

The Co-ordinator,
Seven Days FDTP on
“VLSI Design – EC6601”
Department of Electronics Engineering,
MIT Campus, Anna University,
Chromepet, Chennai – 600044.
E-Mail :  vlsielex17@gmail.com
Mobile: 8015823900

Registration form 

Note :

No Registration fees.
Registration is on First Come – First Served basis only
Only limited number of seats(25) are available.
Selected candidates will be intimated by e-mail.
Preference will be given to Young faculty
No TA/DA will be paid.
No accommodation will be provided.

Dates to remember :

Last date for submission of application : 17/11/2017
Intimation of selection  : 17/11/2017
Confirmation of participation  : 18/11/2017
Training Program : 20/11/2017 to 26/11/2017

Click here for more details