CS2253 & COMPUTER ORGANIZATION AND ARCHITECTURE
UNIT - I
PART-A (2 MARKS)
1. Define the term Computer Architecture.
2. Define Multiprocessing.
3. What is meant by instruction?
4. What is Bus? Draw the single bus structure.
5. Define Pipeline processing.
6. Draw the basic functional units of a computer.
7. Briefly explain Primary storage and secondary storage.
8. What is register?
9. Define RAM.
10. Give short notes on system software.
11. Write down the operation of control unit?
12. Define Memory address register.
13. What is stack & queue?
14. Define Addressing modes.
15. Write the basic performance equation?
16. Define clock rate.
17. List out the various addressing techniques.
18. Draw the flow of Instruction cycle.
19. Suggest about Program counter.
20. List out the types in displacement addressing.
21. What is meant by stack addressing?
22. Define carry propagation delay.
23. Draw a diagram to implement manual multiplication algorithm.
24. Perform the 2’s complement subtraction of smaller number(101011) from larger number(111001).
PART-B (16 Marks)
1. Write briefly about computer fundamental system?
2. Explain memory unit functions.
3. Explain memory locations and addresses.
4. Explain Software interface.
5. Explain instruction set Architecture? Give examples.
6. What is bus explain it in detail?
7. Explain briefly about performance evaluation by using various bench marks. List out the types of bench marks and mention its advantage and disadvantage.
8. Explain the operations of stacks and queues.
9. Discuss about different types of addressing modes.
10. Explain in detail about different instruction types and instruction sequencing.
11. Explain Fixed point representation.
12. How floating point addition is implemented. Explain briefly with a neat diagram.
13. Give the difference between RISC and CISC.
14. Write an algorithm for the division of floating point number and illustrate with an example.
PART-A (2 MARKS)
1. What are the basic operations performed by the processor?
2. Define Data path.
3. Define Processor clock.
4. Define Latency and throughput.
5. Discuss the principle operation of micro programmed control unit.
6. What are the differences between hardwired and micro programmed control units?
7. Define nanoprogramming.
8. What is control store?
9. What are the advantages of multiple bus organization over a single bus organization?
10. Write control sequencing for the executing the instruction. Add R4,R5,R6.
11. What is nano control memory?
12. What is the nano instruction format of Qm-1?
13. What is the capacity of nano control memory?
14. Define micro routine.
15. What is meant by hardwired control?
16. What are the types of micro instruction?
17. Name the methods for generating the control signals.
1. Draw and explain typical hardware control unit.
2. Draw and explain about micro program control unit.
3. Write short notes on
(i)Micro instruction format (ii) Symbolic micro instruction.
4. Explain multiple bus organization in detail.
PART-A (2 MARKS)
1. What is Pipelining?
2. What are the major characteristics of a Pipeline?
3. What are the various stages in a Pipeline execution?
4. What are the types of pipeline hazards?
5. Define structural, data, and control hazard.
6. List two conditions when processor can stall.
7. List the types of data hazards.
8. List the techniques used for overcoming hazard.
9. What is instruction level parallelism?
10. What are the types of dependencies?
11. What is delayed branching?
12. Define deadlock.
13. Draw the hardware organization of two stage pipeline.
14. What is branch prediction?
15. Give two examples for instruction hazard.
16. List the various pipelined processors.
17. Why we need an instruction buffer in a pipelined CPU?
18. What are the problems faced in instruction pipeline?
19. Write down the expression for speedup factor in a pipelined architecture.
PART-B (16 MARKS)
1. Explain different types of hazards that occur in a pipeline.
2. Explain various approaches used to deal with conditional branching.
3. Explain the basic concepts of pipelining and compare it with sequence processing with a neat diagram.
4. Explain instruction pipelining.
5. What is branch hazard? Describe the method for dealing with the branch hazard?
6. What is data hazard? Explain the methods for dealing with data hazard?
7. Explain the function of six segment pipeline and draw a space diagram for six segment pipeline solving the time it takes to process eight tables.
8. Explain the influence of instruction sets.
9. Draw and explain data path modified for pipelined execution.
10. Explain about various exceptions.
UNIT – IV
PART- A (2 MARKS)
1. What is Memory system?
2. Give classification of memory.
3. Define cache.
4. What is Read Access Time?
5. Define Random Access Memory.
6. What are PROMS?
7. Define Memory refreshing.
8. What is SRAM and DRAM?
9. What is volatile memory?
10. Define data transfer or band width.
11. What is flash memory?
12. What is multi level memories?
13. What is address translation page fault routine, page fault and demand paging?
14. What is associate memory?
15. Define Seek time and latency time.
16. What is TLB?
17. Define Magneto Optical disk.
18. Define Virtual memory.
19. What are the enhancements used in the memory management?
20. Define the term LRU and LFU.
21. Define memory cycle time.
22. What is static memories?
23. What is locality of reference?
24. Define set associative cache.
25. What is meant by block replacement?
26. List the advantages of write through cache.
27. Give formula to calculate average memory access time.
28. Define conflict.
29. What is memory interleaving?
30. What is DVD?
31. Give the features of ROM cell.
32. List the difference between static RAM and dynamic RAM.
33. What is disk controller?
34. How a data is organized in the disk?
PART-B (16 MARKS)
1. Illustrate the characteristics of some common memory technologies.
2. Describe in detail about associative memory.
3. Discuss the concept of Memory interleaving and give its advantages.
4. Discuss the different mapping techniques used in cache memories and their relative merits and demerits.
5. Comparing paging and segmentation mechanisms for implementing the virtual memory.
6. What do you mean by virtual memory? Discuss how paging helps in implementing virtual memory.
7. Discuss any six ways of improving the cache performance.
8. Explain the virtual memory translation and TLB with necessary diagram.
PART-A (2 MARKS)
1. Define intra segment and inter segment communication.
2. Mention the group of lines in the system bus.
3. What is bus master and slave master?
4. Differentiate synchronous and asynchronous bus.
5. What is strobe signal?
6. What is bus arbitration?
7. Mention types of bus arbitration.
8. What is I/O control method?
9. What is DMA?
10. Why does the DMA priority over CPU when both request memory transfer?
11. List out the types of interrupts.
12. What is dumb terminal?
13. What is the need for DMA transfer?
14. List down the functions performed by an Input/Output unit.
1. Explain with the block diagram the DMA transfer in a computer system.
2. Describe in detail about IOP Organization.
3. Describe the data transfer method using DMA.
4. Write short notes on the following
(a) Magnetic disk drive
(b) Optial drives.
5. Discuss the design of a typical input or output interface.
6. What are interrupts? How are they handled?
7. Give comparison between memory mapped I/O and I/O mapped I/O.
8. Explain the action carried out by the processor after occurrence of an interrupt.
9. What is DMA? Describe how DMA is used to transfer data from peripherals.
10. Explain various data transfer modes used in DMA.
11. Explain SCSI bus standards.
12. Describe the working principle of USB.