Digital Logic Circuits (DLC)–2marks and 16marks Question Bank


DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

DIGITAL LOGIC CIRCUITS

YEAR : II

SEMESTER : IV


UNIT - I

BOOLEAN ALGEBRA & COMBINATIONAL CIRCUITS


PART-A

1) What is meant by parity bit?

2) What are registers?

3) What is meant by register transfer?

4) Define binary logic?

5) Define logic gates?

6) Define duality property.

7) State De Morgan’s theorem.

8) Reduce A.A’C.

9) Reduce A (A + B).

10) Reduce A’B’C’ + A’BC’ + A’BC.

11) Reduce AB + (AC)’ + AB’C (AB + C).

12) Simplify the following expression Y = (A + B) (A + C’) (B’ + C’).

13) Simplify the following using De Morgan’s theorem.

14) Show that (X + Y’ + XY) (X + Y’) (X’Y) = 0.

15) Prove that ABC + ABC’ + AB’C + A’BC = AB + AC + BC.

16) Convert the given expression in canonical SOP form Y = AC + AB + BC.

17) Convert the given expression in canonical POS form Y = (A + B)(B + C)(A + C).

18) Find the minterms of the logical expression Y = A’B’C’ + A’B’C + A’BC + ABC’

20) Write the maxterms corresponding to the logical expression Y = (A + B + C’)

21) Convert (4021.2)5 to its equivalent decimal.

22) What are called don’t care conditions?

23) Write down the steps in implementing a Boolean function with levels of NAND Gates?

24) Give the general procedure for converting a Boolean expression in to multilevel NAND diagram?

24) What are the basic digital logic gates?

26) What is a Logic gate?

27) Which gates are called as the universal gates? What are its advantages?


PART-B

1. Design a 4-bit binary adder/ subtractor circuit.

a) Basic equations. (4)

b) Comparison of equations. (4)

c) Design using twos complement Circuit diagram. (8)

2. Design a half adder using NAND – NAND logic. (16)

3. Explain how a full adder can be built using two half adders. (16)

4. Design a half adder using at most three NOR gates. (16)

5. Using 8 to 1 multiplexer, realize the Boolean function

T = f(w, x, y, z) = Σ(0,1,2,4,5,7,8,9,12,13) (16)

6. Design a 8421 to gray code converter. (16)

7. Draw the logic diagram of full subtractor and explain its operation. (16)

8. Draw the circuit diagram of NMOS NAND gate and explain its operation. (16)

9. a) Design a full adder circuit using only NOR gates. (4)

b) Draw the circuit of a CMOS two inputs NAND gate (12)


UNIT II SYNCHRONOUS SEQUENTIAL CIRCUITS

PART-A

1. What are the classifications of sequential circuits?

2. Define Flip flop.

3. What are the different types of flip-flop?

4. What is the operation of RS flip-flop?

5. What is the operation of SR flip-flop?

6. What is the operation of D flip-flop?

7. What is the operation of JK flip-flop?

8. What is the operation of T flip-flop?

9. Define race around condition.

10. What is edge-triggered flip-flop?

11. What is a master-slave flip-flop?

12. Define skew and clock skew.

13. What are the different types of shift type?

14. Explain the flip-flop excitation tables for T flip-flop

15. Define sequential circuit?

16. Give the comparison between combinational circuits and sequential circuits.

17. What do you mean by present state?

18. What do you mean by next state?

19. State the types of sequential circuits?

20. What are the types of shift register?


PART-B

1) i) Realize a JK flip flop using SR flip flop. (8)

ii) Realize a SR flip flop using NAND gates and explain its operation. (8)

2) Explain various steps in the analysis of synchronous sequential circuits

with suitable example. (16)

3) i) Distinguish between a combinational logic circuit and a sequential (4)

logic circuit.

ii) Derive the characteristic equation of SR flip flop T1 PG 257. (8)

iii) Using a JK flip flop, explain how a D flip flop can be obtained. (4)

4) Design a four state down counter using T flip flop. (16)

5) Design a 4-bit synchronous 8421 decade counter with ripple carry. (16)

6) Design a synchronous 3-bit gray code up counter with the help of

excitation table. (16)

7) Describe the input and output action of JK master/slave flip flops. (16)

8) D(16esign a MOD-10 synchronous counter using JK flip flops

9) Realize SR neither flip flop using NOR gates and explain its operation. (16)

10) a) Design a 3-bit binary up-down counter. (8)

b) Design a 4-bit UP/DOWN synchronous binary counter.

 

 

11) a)Design a divide by 6 (MOD 6) counter using T flip flop.

 

b) Realize a D flip flop using SR and T flip flops.

 


UNIT III

ASYNCHRONOUS SEQUENTIAL CIRCUITS


PART A

1) Define asynchronous sequential circuit?

2) Give the comparison between synchronous & asynchronous sequential circuits?

3) What are the steps for the design of asynchronous sequential circuit?

4) What is fundamental mode sequential circuit?

5) What are pulse mode circuits?

6) What is the significance of state assignment?

7) When does race condition occur?

8) What are the different techniques used in state assignment?

9) What are the steps for the design of asynchronous sequential circuit?

10) What is hazard?

11) What is static 1 hazard?

12) What are static 0 hazards?

13) What is dynamic hazard?

14) What is the cause for essential hazards?

15) What is SM chart?

16) What are the advantages of SM chart?

17) What is primitive flow chart?

18) What is combinational circuit?

19) What is state equivalence theorem?

20) What do you mean by distinguishing sequences?

21) Prove that the equivalence partition is unique

22) Define compatibility.

23) Define merger graph.


PART B

1. Explain with neat diagram the different hazards and the (16)

way to eliminate them.

2. State with a neat example the method for the minimization

of primitive flow table. (16)

3. a) Explain in detail about Races. (6)

b) Explain the different methods of state assignment . (10)

4. a) Explain the fundamental mode asynchronous sequential circuit. (8)

b) Briefly explain the pulse mode asynchronous sequential circuit. (8)

5.What are the steps in the analysis and design of asynchronous

sequential circuits? Explain with an example. (16)

9. Find a circuit that has no static hazards and implements the

Boolean function F(A,B,C,D) = Σ (0,2,6,7,8,,10,12) . (16)


UNIT IV

PROGRAMMABLE LOGIC DEVICES, MEMORY & LOGIC FAMILIES


PART A

1. Explain ROM.

2. What are the types of ROM?

3. What is programmable logic array? How it differs from ROM?

4. What is mask - programmable?

5. What is field programmable logic array?

6. List the major differences between PLA and PAL

7. Why the input variables to a PAL are buffered

8. Why RAMs are called as Volatile?

9. Define RAM.

10. List the two categories of RAMs.

11. Define Static RAM and dynamic RAM

12. Define a bus.

13. Define Cache memory.

14. Give the feature of flash memory.

15. What are Flash memories?

16. What is a FIFO memory?

17. What is programmable logic array? How it differs from ROM?

18. Give the comparison between PROM and PLA.

19 Classify the logic family by operation?


PART B

1.

a) Explain the operation of bipolar Ram cell with suitable diagram.

 

b) Explain the different types of ROM.

 

2.

What is Ram? Explain the different types of RAM in detail.

 

3.

Draw the circuit of a NMOS two input NOR gate

and explain its operation.

 

4.

Discuss about the TTL parameters. Draw the TTL inverter circuit.

 

5.

a) Draw the circuit of TTL NAND gate and explain its operation.

 

b) Draw the circuit of NMOS NAND gate and explain its operation.

 

6.

Draw the ECL circuit and explain its operation clearly.

 

7.

Explain the totem circuit of TTL logic family.

 



UNIT V

VHDL


PART A

1) Write the acronym for VHDL?

2) What are the different types of modeling VHDL?

3) What is a package and what is the use of these packages

4) What is variable class give example for variable?

5) Name two subprograms and give the difference between these two.

6) What is subprogram overloading?

7) Write the VHDL coding for a sequential statement (d-flip-flop ) entity

8) What are the different kinds of the test bench?

9) What is Moore FSM?

10) Write the test bench for and gate entity.

11) Give the different arithmetic operators?

12) Give the different bitwise operators.

13. Differentiate a signal and variable?

14. Explain ‘case’ statement in VHDL with an Example.

15. Explain ‘BLOCK’ statement in VHDL with an Example.

16. Explain ‘Process’ statement in VHDL with an Example.

17. Explain ‘Generate’ statement in VHDL with an Example.

18. What is Test Bench?

19. Give the behavioral model for JK flip-flop.

20. Give the behavioral model for T flip-flop.


PART B

1. Explain the various modeling methods used in VHDL with an example. (16)

2. Explain in detail about the principal of operation of VHDL Simulator. (16)

3. Write the VHDL program for 4 bit counter. (16)

4. Write the VHDL program for full adder in all three types of modeling? (16)

5. Write VHDL program for 4:1 MUX using behavioral modeling. (16)

6. Write VHDL program for encoder and decoder using structural modeling. (16)

7. With an example explain in detail the test bench creation. (16)

8. Write a verilog program for

1) Full Adder. (8)

2) Shift Register. (8)