Anna University, Chennai
QUESTION BANK
ACADEMIC YEAR 2013 2014 / ODD SEMESTER
Subject Code: EC2203
Subject Name: Digital Electronics Year / Sem: II/III
UNIT  I
MINIMIZATION TECHNIQUES AND LOGIC GATES PARTA (2 MARKS)
1. Write the names of basic logical operators.
1. NOT / INVERT
2. AND
3. OR
2. What are basic properties of Boolean algebra?

3. State the associative property of boolean algebra.
The associative property of Boolean algebra states that the OR ing of several variables results in the same regardless of the grouping of the variables. The associative property is stated as follows:
A+ (B+C) = (A+B) +C
4. State the commutative property of Boolean algebra.
The commutative property states that the order in which the variables are OR ed makes no difference. The commutative property is: A+B=B+A
5. State the distributive property of Boolean algebra.
The distributive property states that AND ing several variables and OR ing the result with a single variable is equivalent to OR ing the single variable with each of the the several variables and then AND ing the sums. The distributive property is:
A+BC= (A+B) (A+C)
6. State the absorption law of Boolean algebra.
The absorption law of Boolean algebra is given by X+XY=X, X(X+Y) =X.
7. State De Morgan's theorem.
De Morgan suggested two theorems that form important part of Boolean algebra. They are,
1) The complement of a product is equal to the sum of the complements.
(AB)' = A' + B'
2) The complement of a sum term is equal to the product of the complements. (A + B)' = A'B'
8. Reduce A.A'C
A.A'C = 0.C [A.A' = 1]
= 0
9. Reduce A(A + B)
A(A + B) = AA + AB
= A(1 + B) [1 + B = 1]
= A.
10. Reduce A'B'C' + A'BC' + A'BC
A'B'C' + A'BC' + A'BC = A'C'(B' + B) + A'B'C
= A'C' + A'BC [A + A' = 1]
= A'(C' + BC)
= A'(C' + B) [A + A'B = A + B]
11. Reduce AB + (AC)' + AB'C(AB + C)
AB + (AC)' + AB'C(AB + C) = AB + (AC)' + AAB'BC + AB'CC
= AB + (AC)' + AB'CC [A.A' = 0]
= AB + (AC)' + AB'C [A.A = 1]
= AB + A' + C' =AB'C [(AB)' = A' + B']
= A' + B + C' + AB'C [A + AB' = A + B]
= A' + B'C + B + C' [A + A'B = A + B]
= A' + B + C' + B'C
=A' + B + C' + B'
=A' + C' + 1
= 1 [A + 1 =1]
12. Simplify the following expression Y = (A + B)(A + C' )(B' + C' )
Y = (A + B)(A + C' )(B' + C' )
= (AA' + AC +A'B +BC )(B' + C') [A.A' = 0]
= (AC + A'B + BC)(B' + C' )
= AB'C + ACC' + A'BB' + A'BC' + BB'C + BCC'

13. Show that (X + Y' + XY)( X + Y')(X'Y) = 0
(X + Y' + XY)( X + Y')(X'Y) = (X + Y' + X)(X + Y' )(X' + Y) [A + A'B = A + B]
= (X + Y' )(X + Y' )(X'Y) [A + A = 1]
= (X + Y' )(X'Y) [A.A = 1]
= X.X' + Y'.X'.Y
= 0 [A.A' = 0]
14. Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC
ABC + ABC' + AB'C + A'BC=AB(C + C') + AB'C + A'BC
=AB + AB'C + A'BC
=A(B + B'C) + A'BC
=A(B + C) + A'BC
=AB + AC + A'BC
=B(A + C) + AC
=AB + BC + AC
=AB + AC +BC ...Proved
15. Convert the given expression in canonical SOP form Y = AC + AB + BC
Y = AC + AB + BC
=AC(B + B' ) + AB(C + C' ) + (A + A')BC
=ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC
=ABC + ABC' +AB'C + AB'C' [A + A =1]
16. Define duality property.
Duality property states that every algebraic expression deducible from the postulates of Boolean algebra remains valid if the operators and identity elements are interchanged. If the dual of an algebraic expression is desired, we simply interchange OR and AND operators and replace 1's by 0's and 0's by 1's.
17. Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x(y'z' + yz). By applying DeMorgan's theorem.
F1' = (x'yz' + x'y'z)' = (x'yz')'(x'y'z)' = (x + y' + z)(x + y +z') F2' = [x(y'z' + yz)]' = x' + (y'z' + yz)'
= x' + (y'z')'(yz)'
= x' + (y + z)(y' + z')
18. Simplify the following expression
Y = (A + B) (A = C) (B + C)
= (A A + A C + A B + B C) (B + C)
= (A C + A B + B C) (B + C)
= A B C + A C C + A B B + A B C + B B C + B C C
= A B C
19. What are the methods adopted to reduce Boolean function?
i) Karnaug map
ii) Tabular method or QuineMcCluskey method iii) Variable entered map technique.
20.State the limitations of karnaugh map.
i) Generally it is limited to six variable map (i.e) more then six variable involving expression are not reduced.
ii) The map method is restricted in its capability since they are useful for simplifying only Boolean expression represented in standard form.
21. What is a karnaugh map?

22. Find the minterms of the logical expression Y = A'B'C' + A'B'C + A'BC + ABC'
Y = A'B'C' + A'B'C + A'BC + ABC'
=m0 + m1 +m3 +m6
=_m(0, 1, 3, 6)
23. Write the maxterms corresponding to the logical expression
Y = (A + B + C' )(A + B' + C')(A' + B' + C)
= (A + B + C' )(A + B' + C')(A' + B' + C)
=M1.M3.M6
=_ M(1,3,6)
24. What are called don’t care conditions?
In some logic circuits certain input conditions never occur, therefore the corresponding output never appears. In such cases the output level is not defined, it can be either high or low. These output levels are indicated by ‘X’ or‘d’ in the truth tables and are called don’t care conditions or incompletely specified functions.
25. What is a prime implicant?
A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map.
26. What is an essential implicant?
If a min term is covered by only one prime implicant, the prime implicant is said to be essential
27. What is a Logic gate?
Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function.
28.Give the classification of logic families
Bipolar Unipolar
Saturated Non Saturated PMOS NMOS
CMOS
RTL Schottky TTL ECL DTL
I I C TTL
29. What are the basic digital logic gates?
The three basic logic gates are
AND gate OR gate NOT gate
30. Which gates are called as the universal gates? What are its advantages?
The NAND and NOR gates are called as the universal gates. These gates are used to perform any type of logic application.
31.Classify the logic family by operation?
The Bipolar logic family is classified into
Saturated logic
Unsaturated logic.
The RTL, DTL, TTL, I2L, HTL logic comes under the saturated logic family. The Schottky TTL, and ECL logic comes under the unsaturated logic family.
32..State the classifications of FET devices.
FET is classified as
1. Junction Field Effect Transistor (JFET)

33. Mention the classification of saturated bipolar logic families.
The bipolar logic family is classified as follows: RTL Resistor Transistor Logic
DTL Diode Transistor logic I2L Integrated Injection Logic TTL Transistor Transistor Logic ECL Emitter Coupled Logic
34.Mention the different IC packages?
DIP Dual in line package
LCC Leadless Chip Carrier
PLCC Plastic Leaded Chip carrier PQFP Plastic Quad Flat Pack PGA Pin Grid Array
35. Mention the important characteristics of digital IC’s?
Fan out
Power dissipation Propagation Delay Noise Margin
Fan In
Operating temperature
Power supply requirements
36. Define Fanout?
Fan out specifies the number of standard loads that the output of the gate can drive with out impairment of its normal operation.
37. Define power dissipation?
Power dissipation is measure of power consumed by the gate when fully driven by all its inputs.
38. What is propagation delay?
Propagation delay is the average transition delay time for the signal to propagate from input to output when the signals change in value. It is expressed in ns.
39. Define noise margin?
It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output. It is expressed in volts.
40. Define fan in?
Fan in is the number of inputs connected to the gate without any degradation in thevoltage level.
41. What is Operating temperature?
All the gates or semiconductor devices are temperature sensitive in nature. The temperature in which the performance of the IC is effective is called as operating temperature. Operating temperature of the IC vary from 00 C to 700 c.
42. What is High Threshold Logic?
Some digital circuits operate in environments, which produce very high noise signals. For operation in such surroundings there is available a type of DTL gate which possesses a high threshold to noise immunity. This type of gate is called HTL logic or High Threshold Logic.
43. What are the types of TTL logic?
1. Open collector output
2. TotemPole Output
3. Tristate output.

If the channel is initially doped lightly with ptype impurity a conducting channel exists at zero gate voltage and the device is said to operate in depletion mode.
45. What is enhancement mode operation of MOS?
If the region beneath the gate is left initially uncharged the gate field must induce achannel before current can flow. Thus the gate voltage enhances the channel current and such a device is said to operate in the enhancement mode.
46. Mention the characteristics of MOS transistor?
1. The n channel MOS conducts when its gate to source voltage is positive.
2. The p channel MOS conducts when its gate to source voltage is negative
3. Either type of device is turned of if its gate to source voltage is zero.
47. How schottky transistors are formed and state its use?
A schottky diode is formed by the combination of metal and semiconductor. The presence of schottky diode between the base and the collector prevents the transistor from going into saturation. The resulting transistor is called as schottky transistor.
The use of schottky transistor in TTL decreases the propagation delay without a sacrifice of power dissipation.
48. List the different versions of TTL
1.TTL (Std.TTL) 2.LTTL (Low Power TTL)
3.HTTL (High Speed TTL) 4.STTL (Schottky TTL)
5.LSTTL (Low power Schottky TTL)
49. Why totem pole outputs cannot be connected together.
Totem pole outputs cannot be connected together because such a connection might produce excessive current and may result in damage to the devices.
50. State advantages and disadvantages of TTL Adv:
Easily compatible with other ICs
Low output impedance
Disadv:
Wired output capability is possible only with tristate and open collector types
Special circuits in Circuit layout and system design are required.
51. When does the noise margin allow digital circuits to function properly.
When noise voltages are within the limits of VNA(High State Noise Margin) and
VNK
for a particular logic family.
52. What happens to output when a tristate circuit is selected for high impedance.
Output is disconnected from rest of the circuits by internal circuitry.
53. What is 14000 series.
It is the oldest and standard CMOS family. The devices are not pin compatible or electrically compatible with any TTL Series.
54. Simplify the following using De Morgan's theorem [((AB)'C)'' D]'
[((AB)'C)'' D]' = ((AB)'C)'' + D' [(AB)' = A' + B']
= (AB)' C + D'
= (A' + B' )C + D'

1. Reduce the expression F = m(1,,6,12,13,14) + d(2,4) is SOP and POS forms.
2. Determine the prime implicants of the function

3. Simplify the Boolean function using Kmap. F(A,B,C,D,E) = (0,2,4,6,9,13,21,23,25,29,31)
4. Reduce the following function using Kmap technique

5. Reduce the following function using kmap technique

6. Implement F=((A+B).(C+D))' + A using NAND gates and NOR gates only.
7. Explain TTL with neat diagrams.
8. Discuss all the characteristics of digital IC's.
9. Explain in detail about Schottky TTL.
10. Explain with neat diagrams ECL.
11. Explain with necessary diagrams MOS
12. Explain in detail about interfacing CMOS and TTL device
13. Give the comparison between TTL and CMOS families
UNIT  II COMBINATIONAL CIRCUITS

1. Define combinational logic
When logic gates are connected together to produce a specified output for certain specified combinations of input variables, with no storage involved, the resulting circuit is called combinational logic.
2. Explain the design procedure for combinational circuits
The problem definition
Determine the number of available input variables & required O/P variables. Assigning letter symbols to I/O variables
Obtain simplified Boolean expression for each O/P.
Obtain the logic diagram.
3. Define Half adder and full adder
The logic circuit that performs the addition of two bits is a half adder. The circuit that performs the addition of three bits is a full adder.
4. Define Decoder?
A decoder is a multiple  input multiple output logic circuit that converts coded
inputs into coded outputs where the input and output codes are different.
5. What is binary decoder?
A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n out puts lines.
6. Define Encoder?
An encoder has 2n input lines and n output lines. In encoder the output lines generate the binary code corresponding to the input value.
7. What is priority Encoder?
A priority encoder is an encoder circuit that includes the priority function. In priorityencoder, if 2 or more inputs are equal to 1 at the same time, the input having the highestpriority will take precedence.
8. Define multiplexer?
Multiplexer is a digital switch. If allows digital information from several sources to be routed onto a single output line.

A comparator is a special combinational circuit designed primarily to compare the relative magnitude of two binary numbers.
9. List basic types of programmable logic devices.
. Read only memory
. Programmable logic Array
. Programmable Array Logic
10. Define ROM
Read only memory is a device that includes both the decoder and the OR gates within a single IC package.
11. Define address and word:
In a ROM, each bit combination of the input variable is called on address. Each bitcombination that comes out of the output lines is called a word.
12. State the types of ROM
. Masked ROM.
. Programmable Read only Memory
. Erasable Programmable Read only memory.
. Electrically Erasable Programmable Read only Memory.
13. What is programmable logic array? How it differs from ROM?
In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.
14. Which gate is equal to ANDinvert Gate?
NAND gate.
15. Which gate is equal to ORinvert Gate?
NOR gate.
16. Bubbled OR gate is equal to
NAND gate
17. Bubbled AND gate is equal to
NOR gate
PARTB (16 MARKS)
1. Explain the working of BCD Ripple Counter with the help of state diagram and logic diagram
2. Design a logic circuit to convert the BCD code to Excess  3 codes.
3. Explain the carry lookahead adder
4. Explain the BCD adder with examples
5. Explain the any two code converters.
UNIT III SEQUENTIAL CIRCUITS
PARTA (2 MARKS)
1. What are the classification of sequential circuits?
The sequential circuits are classified on the basis of timing of their signals into twotypes. They are,
1)Synchronous sequential circuit.
2)Asynchronous sequential circuit.

The basic unit for storage is flip flop. A flipflop maintains its output state either at
1or 0 until directed by an input signal to change its state.
3. What are the different types of flipflop?
There are various types of flip flops. Some of them are mentioned below they are,
Ã¼ RS flipflop
Ã¼ SR flipflop
Ã¼ D flipflop
Ã¼ JK flipflop
Ã¼ T flipflop
4. What is the operation of RS flipflop?
Ã¼ When R input is low and S input is high the Q output of flipflop is set.
Ã¼ When R input is high and S input is low the Q output of flipflop is reset.
Ã¼ When both the inputs R and S are low the output does not change
Ã¼ When both the inputs R and S are high the output is unpredictable.
5. What is the operation of SR flipflop?
Ã¼ When R input is low and S input is high the Q output of flipflop is set.
Ã¼ When R input is high and S input is low the Q output of flipflop is reset.
Ã¼ When both the inputs R and S are low the output does not change.
Ã¼ When both the inputs R and S are high the output is unpredictable.
6. What is the operation of D flipflop?
In D flipflop during the occurrence of clock pulse if D=1, the output Q is set and if
D=0, the output is reset.
7. What is the operation of JK flipflop?
Ã˜ When K input is low and J input is high the Q output of flipflop is set.
Ã˜ When K input is high and J input is low the Q output of flipflop is reset.
Ã˜ When both the inputs K and J are low the output does not change
Ã˜ When both the inputs K and J are high it is possible to set or reset the flipflop (ie) the output toggle on the next positive clock edge.
8. What is the operation of T flipflop?
T flipflop is also known as Toggle flipflop.
Ã˜ When T=0 there is no change in the output.
Ã˜ When T=1 the output switch to the complement state (ie) the output toggles.
9. Define race around condition.
results
In JK flipflop output is fed back to the input. Therefore change in the output
change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called ‘race around condition’.
10. What is edgetriggered flipflop?
The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flipflop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive to its inputs only at this transition of theclock.
11. What is a masterslave flipflop?
A masterslave flipflop consists of two flipflops where one circuit serves as a masterand the other as a slave.
12.Define rise time.
The time required to change the voltage level from 10% to 90% is known as rise time(tr).
13. Define fall time.
The time required to change the voltage level from 90% to 10% is known as fall time(tf).
14. Define skew and clock skew.
The phase shift between the rectangular clock waveforms is referred to as skew and the time delay between the two clock pulses is called clock skew.
15. Define setup time.
The setup time is the minimum time required to maintain a constant voltage levels at the excitation inputs of the flipflop device prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as tsetup.
16. Define hold time.
The hold time is the minimum time for which the voltage levels at the excitation inputs must remain constant after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as thold.
17. Define propagation delay.
A propagation delay is the time required to change the output after the application of the input.
18. Define registers.
A register is a group of flipflops flipflop can store one bit information. So an nbit register has a group of n flipflops and is capable of storing any binary information/number
containing nbits.
19. Define shift registers.
The binary information in a register can be moved from stage to stage within the register or into or out of the register upon application of clock pulses. This type of bit movement or shifting is essential for certain arithmetic and logic operations used in microprocessors. This gives rise to group of registers called shift registers.
20. What are the different types of shift type?
There are five types. They are,
Ã˜ Serial In Serial Out Shift Register
Ã˜ Serial In Parallel Out Shift Register
Ã˜ Parallel In Serial Out Shift Register
Ã˜ Parallel In Parallel Out Shift Register
Ã˜ Bidirectional Shift Register
21. Explain the flipflop excitation tables for RS FF.
RS flipflop
In RS flipflop there are four possible transitions from the present state to the next state. They are,
Ã˜ 0_0 transition: This can happen either when R=S=0 or when R=1 and
S=0.
Ã˜ 0_1 transition: This can happen only when S=1 and R=0.
Ã˜ 1_0 transition: This can happen only when S=0 and R=1.
Ã˜ 1_1 transition: This can happen either when S=1 and R=0 or S=0 and
R=0.
22. Explain the flipflop excitation tables for JK flipflop
In JK flipflop also there are four possible transitions from present state to next
state.
They are,
Ã˜ 0_0 transition: This can happen when J=0 and K=1 or K=0.
Ã˜ 0_1 transition: This can happen either when J=1 and K=0 or when
J=K=1.
Ã˜ 1_0 transition: This can happen either when J=0 and K=1 or when
J=K=1.
Ã˜ 1_1 transition: This can happen when K=0 and J=0 or J=1.
23. Explain the flipflop excitation tables for D flipflop
In D flipflop the next state is always equal to the D input and it is independent of the present state. Therefore D must be 0 if Qn+1 has to 0,and if Qn+1 has to be 1 regardless the value of Qn.
24. Explain the flipflop excitation tables for T flipflop
When input T=1 the state of the flipflop is complemented; when T=0,the state of the flipflop remains unchanged. Therefore, for 0_0 and 1_1 transitions T must be 0 and for 0_1 and 1_0 transitions must be 1.
25. Define sequential circuit?
In sequential circuits the output variables dependent not only on the present input variables but they also depend up on the past history of these input variables.
26. Give the comparison between combinational circuits and sequential circuits.
Ã˜ Combinational circuits Sequential circuits
Ã˜ Memory unit is not required Memory unity is required
Ã˜ Parallel adder is a combinational circuit Serial adder is a sequential circuit
27. What do you mean by present state?
The information stored in the memory elements at any given time define.s the present state of the sequential circuit.
28. What do you mean by next state?
The present state and the external inputs determine the outputs and the next state of the sequential circuit.
29. State the types of sequential circuits?
1. Synchronous sequential circuits
2. Asynchronous sequential circuits
30. Define synchronous sequential circuit
In synchronous sequential circuits, signals can affect the memory elements only atdiscrete instant of time.
31. Define Asynchronous sequential circuit?
In asynchronous sequential circuits change in input signals can affect memory element at any instant of time.
32. Give the comparison between synchronous & Asynchronous sequential circuits?
Synchronous sequential circuits Asynchronous sequential circuits.
Memory elements are clocked flipflops Memory elements are either unlocked flip  flops or time delay elements.
Easier to design More difficult to design
33. Define flipflop
Flip  flop is a sequential device that normally samples its inputs and changes its outputs only at times determined by clocking signal.
34. Draw the logic diagram for SR latch using two NOR gates.
35. The following wave forms are applied to the inputs of SR latch. Determine the
Qwaveform Assume initially Q = 1
Here the latch input has to be pulsed momentarily to cause a change in the latch output state, and the output will remain in that new state even after the input pulse is over.

In the JK latch, the output is feedback to the input, and therefore changes in the output results change in the input. Due to this in the positive half of the clock pulse if J and K are both high then output toggles continuously. This condition is known as race aroundcondition.
37. What are the types of shift register?
1. Serial in serial out shift register?
2. Serial in parallel out shift register
3. Parallel in serial out shift register
4. Parallel in parallel out shift register
5. Bidirectional shift register shift register
38. State the types of counter?
1. Synchronous counter
2. Asynchronous Counter
39. Give the comparison between synchronous & Asynchronous counters.
Asynchronous counters
Ã˜ In this type of counter flipflops are connected in such a way that output of 1st
flipflop drives the clock for the next flipflop.
Ã˜ All the flipflops are Not clocked Simultaneously
Synchronous counters
Ã˜ In this type there is no connection between
output of first flipflop and clock input of the next flip  flop
Ã˜ All the flipflops are clocked simultaneously
40. The t pd for each flipflop is 50 ns. Determine the maximum operating frequency forMOD  32 ripple counter
f max (ripple) = 5 x 50 ns = 4 MHZ
PARTB (16 MARKS)
1. Explain the analysis of clocked sequential circuits with examples
2. Design an asynchronous sequential circuit with 2 inputs T and C. The output attains a value of1 whenT = 1 & C moves from 1 to 0. Otherwise the output is 0.
3. A asynchronous sequential machine has one input line where 0's and 1's are being incident. The machine has to produce a output of 1 only when exactly two 0's are followed by a '1' or exactly two
1's are followed by a '0'.Using any state assignment and JK flipflop, synthesize themachine
4. Design an asynchronous sequential circuit with 2 inputs X and Y and with one output Z Wherever
Y is 1, input X is transferred to Z .When Y is 0; the output does not change for anychange in
X.Use SR latch for implementation of the circuit
5. Develop the state diagram and primitive flow table for a logic system that has 2 inputs,x and y and an output z.And reduce primitive flow table. The behavior of the circuit is stated as follows.
Initially x=y=0. Whenever x=1 and y = 0 then z=1, whenever x = 0 and y = 1 then z = 0.When
x=y=0 or x=y=1 no change in z ot remains in the previous state. The logic system has edge triggered inputs with out having a clock .the logic system changes state on the rising edges of the2 inputs. Static input values are not to have any effect in changing the Z output
6. Design an asynchronous sequential circuit with two inputs X and Y and with one output Z.
Whenever Y is 1, input X is transferred to Z.When Y is 0,the output does not change for any
Changein X.
7. Obtain the primitive flow table for an asynchronous circuit that has two inputs x,y and one output
Z. An output z =1 is to occur only during the input state xy = 01 and then if the only if the input state xy =01 is preceded by the input sequence.
8. A pulse mode asynchronous machine has two inputs. It produces an output whenever two
consecutive pulses occur on one input line only .The output remains at '1' until a pulse has occurred on the other input line. Draw the state table for the machine.
9. Construct the state diagram and primitive flow table for an asynchronous network that has two inputs and one output. The input sequence X1X2 = 00,01,11 causes the output to become 1.The
next input change then causes the output to return to 0.No other inputs will produce a 1 output.
10. Draw the state diagram and characteristics equation of T FF, D FF and JK FF
11. Design and explain the working of a synchronous mod  7 counter
12.Design a synchronous counter for 4>6>7>3>1>4 avoid lockout condition, use JK type design
13. Design and explain the working of a synchronous mod 3 counter
14.Design a 2 bit up/ down counter using T flip flops. Implement using synchronous design. (16)
15. Explain in detail about (SISO, PISO and PIPO) shift register.
1. Explain ROM
UNITIV MEMORY DEVICES PARTA (2 MARKS)
A read only memory(ROM) is a device that includes both the decoder and the OR gates within a single IC package. It consists of n input lines and m output lines. Each bit combination of the input variables is called an address. Each bit combination that comes out of the output lines is called a word. The number of distinct addresses possible with n input variables is 2n.
2. What are the types of ROM?
1.PROM
2.EPROM
3.EEPROM
3. Explain PROM.
PROM (Programmable Read Only Memory)
It allows user to store data or program. PROMs use the fuses with material likenichrome and polycrystalline. The user can blow these fuses by passing
around 20 to 50 mA of current for the period 5 to 20Âµs.The blowing of fuses is called programming of ROM. The PROMs are one time programmable. Once programmed, the information is stored permanent.
4. Explain EPROM.
EPROM(Erasable Programmable Read Only Memory)
EPROM use MOS circuitry. They store 1’s and 0’s as a packet of charge in a
buried layer of the IC chip. We can erase the stored data in the EPROMs by
exposing the chip to ultraviolet light via its quartz window for 15 to 20 minutes. It is not possible to erase selective information. The chip can be reprogrammed.
5. Explain EEPROM.
EEPROM(Electrically Erasable Programmable Read Only Memory) EEPROM also use MOS circuitry. Data is stored as charge or no charge on an insulated layer or an insulated floating gate in the device. EEPROM allows selective erasing at the register level rather than erasing all the information since the information can be changed by using electrical signals.
6. What is RAM?
Random Access Memory. Read and write operations can be carried out.
7. Define ROM
A read only memory is a device that includes both the decoder and the OR gates within a single IC package.
8. Define address and word:
In a ROM, each bit combination of the input variable is called on address. Each bitcombination that comes out of the output lines is called a word.
9. What are the types of ROM.
1. Masked ROM.
2. Programmable Read only Memory
3. Erasable Programmable Read only memory.
4. Electrically Erasable Programmable Read only Memory.
10. What is programmable logic array? How it differs from ROM?
In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.
11. What is mask  programmable?
With a mask programmable PLA, the user must submit a PLA program table to themanufacturer.
12. What is field programmable logic array?
The second type of PLA is called a field programmable logic array. The user by means of certain recommended procedures can program the EPLA.
13. List the major differences between PLA and PAL
PLA:
Both AND and OR arrays are programmable and Complex
Costlier than PAL PAL
AND arrays are programmable OR arrays are fixed
Cheaper and Simpler
14. Define PLD.
Programmable Logic Devices consist of a large array of AND gates and OR
gates that can be programmed to achieve specific logic functions.
15. Give the classification of PLDs.
PLDs are classified as PROM(Programmable Read Only Memory), ProgrammableLogic Array(PLA), Programmable Array Logic (PAL), and Generic Array Logic(GAL)
16. Define PROM.
PROM is Programmable Read Only Memory. It consists of a set of fixed AND
gates connected to a decoder and a programmable OR array.
17. Define PLA
PLA is Programmable Logic Array(PLA). The PLA is a PLD that consists of a programmable AND array and a programmable OR array.
18. Define PAL
PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR array with output logic.
19. Why was PAL developed ?
It is a PLD that was developed to overcome certain disadvantages of PLA, such aslonger delays due to additional fusible links that result from using two programmable arrays and more circuit complexity.
20. Define GAL
GAL is Generic Array Logic. GAL consists of a programmable AND array and a fixed OR array with output logic.
21. Give the feature of flash memory.
The ideal memory has high storage capacity, nonvolatility; insystem read and write capability, comparatively fast operation. The traditional memory technologies such as ROM, PROM, EEPROM individually exhibits one of these characteristics, but no single technology has all of them except the flash memory.
22. What are Flash memories?
They are high density read/write memories that are nonvolatile, which means datacan be stored indefinitely with out power.
23. List the three major operations in a flash memory.
Programming, Read and Erase operation
24. What is a FIFO memory?
The term FIFO refers to the basic operation of this type of memory in which the first data bit written into the memory is to first to be read out.
25. List basic types of programmable logic devices.
1. Read only memory
2. Programmable logic Array
3. Programmable Array Logic
26. Define ROM
A read only memory is a device that includes both the decoder and the OR gates
Within a single IC package.
27. Define address and word:
In a ROM, each bit combination of the input variable is called on address. Each bitcombination that comes out of the output lines is called a word.
28. What are the types of ROM?
1. Masked ROM.
2. Programmable Read only Memory
3. Erasable Programmable Read only memory.
4. Electrically Erasable Programmable Read only Memory.
29. What is programmable logic array? How it differs from ROM?
In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.
30. What is mask  programmable?
With a mask programmable PLA, the user must submit a PLA PLA program table to the manufacturer.
31. Give the comparison between PROM and PLA.
PROM PLA
1. And array is fixed and OR Both AND and OR arrays are array is programmable. Programmable.
2. Cheaper and simple to use. Costliest and complex than PROMS.
32. Give the feature of UV EPROM
UV EPROM is electrically programmable by the user, but the store data must be erased by exposure to ultra violet light over a period of several minutes.
33. Why the input variables to a PAL are buffered
The input variables to a PAL are buffered to prevent loading by the large number ofAND gate inputs to which available or its complement can be connected.
34. What does PAL 10L8 specify?
PAL  Programmable Logic Array
10  Ten inputs
L  Active LOW Ouput
8  Eight Outputs
35. What is CPLD?
CPLDs are Complex Programmable Logic Devices. They are larger versions of PLDs with a centralized internal interconnect matrix used to connect the device macro cells together.
36. Define bit, byte and word.
The smallest unit of binary data is bit. Data are handled in a 8 bit unit called byte. Acomplete unit of information is called a word which consists of one or more bytes.
37. How many words can a 16x8 memory can store?
A 16x8 memory can store 16,384 words of eight bits each
38. Define address of a memory.
The location of a unit of data in a memory is called address.
39. Define Capacity of a memory.
It is the total number of data units that can be stored.
40. What is Read and Write operation?
The Write operation stores data into a specified address into the memory and the
Read operation takes data out of a specified address in the memory.
41. Why RAMs are called as Volatile?
RAMs are called as Volatile memories because RAMs lose stored data when the power is turned OFF.
42. Define ROM.
ROM is a type of memory in which data are stored permanently or semi permanently.Data can be read from a ROM, but there is no write operation
43. Define RAM.
RAM is Random Access Memory. It is a random access read/write memory. The data can be read or written into from any selected address in any sequence.
44. List the two categories of RAMs.
The two categories of RAMs are static RAM (SRAM) and dynamic RAM (DRAM).
45. Define Static RAM and dynamic RAM
Static RAM use flip flops as storage elements and therefore store data indefinitely as long as dc power is applied.
Dynamic RAMs use capacitors as storage elements and cannot retain data very long without capacitors being recharged by a process called refreshing.
46. List the two types of SRAM
Asynchronous SRAMs and Synhronous Burst SRAMs
47. List the basic types of DRAsM
Fast Page Mode DRAM,Extended Data Out DRAM(EDO DRAM),Burst EDO DRAM and Synchronous DRAM.
48. Define a bus
A bus is a set of conductive paths that serve to interconnect two or more functionalcomponents of a system or several diverse systems.
49. Define Cache memory
It is a relatively small, highspeed memory that can store the most recently used instructions or data from larger but slower main memory.
50. What is the technique adopted by DRAMs.
DRAMs use a technique called address multiplexing to reduce the number of address lines.
PART  B (16 MARKS)
1. Explain in detail about PLA with a specific example.
2. Explain with neat diagrams RAM architecture.
3. Explain in detail about PLA and PAL.
4. Explain with neat diagrams a ROM architecture.
5. Explain in detail about RAM organization 6. Explain the static RAM and dynamic
DAM.
7. Explain and draw the memory cycles and timing waveforms
8. Details briefly about Field programmable gate arrays
9. Explain in detail about memory decoding
UNITV PARTA (2 MARKS)
1. What are secondary variables?
Ã˜ present state variables in asynchronous sequential circuits
2. What are excitation variables?
Ã˜ next state variables in asynchronous sequential circuits
3. What is fundamental mode sequential circuit?
Input variables changes if the circuit is stable inputs are levels, not pulses only one input can change at a given time
4. What are pulse mode circuit?
Inputs are pulses width of pulses are long for circuit to respond to the input pulse width must not be so long that it is still present after the new state is reached
5. What is the significance of state assignment?
Ã˜ In synchronous circuitsstate assignments are made with the objective of circuit reduction
Ã˜ Asynchronous circuitsits objective is to avoid critical races
6. When do race condition occur?
Ã˜ two or more binary state variables change their value in response to the change in i/p variable
7. What is non critical race?
Ã˜ final stable state does not depend on the order in which the state variable changes
Ã˜ race condition is not harmful
8. What is critical race?
Ã˜ final stable state depends on the order in which the state variable changes
Ã˜ race condition is harmful
9. When does a cycle occur?
Ã˜ asynchronous circuit makes a transition through a series of unstable state
10. What are the different techniques used in state assignment?
Ã˜ shared row state assignment
Ã˜ one hot state assignment
11.What are the steps for the design of asynchronous sequential circuit?
Ã˜ construction of primitive flow table
Ã˜ reduction of flow table
Ã˜ state assignment is made
Ã˜ ealization of primitive flow table
12. What is hazard?
Ã˜ unwanted switching transients
13. What is static 1 hazard?
Ã˜ output goes momentarily 0 when it should remain at 1
14. What is static 0 hazard?
Ã˜ output goes momentarily 1 when it should remain at 0
15. What is dynamic hazard?
Ã˜ output changes 3 or more times when it changes from 1 to 0 or 0 to 1
16. What is the cause for essential hazards?
Ã˜ unequal delays along 2 or more path from same input
17. What is flow table?
Ã˜ state table of an synchronous sequential network
18. What is SM chart?
Ã˜ describes the behavior of a state machine
Ã˜ used in hardware design of digital systems
19. What are the advantages of SM chart?
Ã˜ easy to understand the operation
Ã˜ east to convert to several equivalent forms
20. What is primitive flow chart?
Ã˜ one stable state per row
21. What is combinational circuit?
Ã˜ Output depends on the given input. It has no storage element.
22. What is state equivalence theorem ?
Two states SA and SB, are equivalent if and only if for every possible input X
sequence, the outputs are the same and the next states are equivalent i.e., if SA (t + 1) = SB (t + 1) and ZA = ZB then SA = SB.
23. What do you mean by distinguishing sequences?
Two states, SA and SB of sequential machine are distinguishable if and only if their exists at least one finite input sequence. Which, when applied to sequential machine causes different output sequences depending on whether SA or SB is the initial state.
24. Prove that the equivalence partition is unique
Consider that there are two equivalence partitions exists : PA and PB, and PA ) PB.This states that, there exist 2 states Si &Sj which are in the same block of one partition and not in the same block of the other. If Si &Sj are in different blocks of say PB, there exists at least on input sequence which distinguishes Si &Sj and therefore, they cannot be in the same block of PA.
25. Define compatibility
States Si and Sj said to be compatible states, if and only if for every input sequence that affects the two states, the same output sequence, occurs whenever both outputs are specified and regardless of whether Si on Sj is the initial state.
26. Define merger graph.
The merger graph is defined as follows. It contains the same number of vertices as the state table contains states. A line drawn between the two state vertices indicates each
compatible state pair. It two states are incompatible no connecting line is drawn.
27. Define incompatibility
The states are said to be incompatible if no line is drawn in between them. If implied states are incompatible, they are crossed & the corresponding line is ignored.
28. Explain the procedure for state minimization.
1. Partition the states into subsets such that all states in the same subsets are 1  equivalent.
2. Partition the states into subsets such that all states in the same subsets are 2  equivalent.
3. Partition the states into subsets such that all states in the same subsets are 3  equivalent.
29. Define closed covering
A Set of compatibles is said to be closed if, for every compatible contained in the set, all its implied compatibles are also contained in the set. A closed set of compatibles, which contains all the states of M, is called a closed covering.
30. Define machine equivalence
Two machines, M1 and M2 are said to be equivalent if and only if, for every state in
M1, there is a corresponding equivalent state in M2 & vice versa.
31. Define state table.
For the design of sequential counters we have to relate present states and next states. The table, which represents the relationship between present states and next states, is called state table.
32. Define total state
The combination of level signals that appear at the inputs and the outputs of the delays define what is called the total state of the circuit.
33. What are the steps for the design of asynchronous sequential circuit?
1. Construction of a primitive flow table from the problem statement.
2. Primitive flow table is reduced by eliminating redundant states using the state reduction
3. State assignment is made
4. The primitive flow table is realized using appropriate logic elements.
34. Define primitive flow table :
It is defined as a flow table which has exactly one stable state for each row in the table. The design process begins with the construction of primitive flow table.
35. What are the types of asynchronous circuits ?
1. Fundamental mode circuits
2. Pulse mode circuits
36. Give the comparison between state Assignment Synchronous circuit and state assignmentasynchronous circuit.
In synchronous circuit, the state assignments are made with the objective of circuit reduction. In asynchronous circuits, the objective of state assignment is to avoid critical
races.
37. What are races?
When 2 or more binary state variables change their value in response to a change in an input variable, race condition occurs in an asynchronous sequential circuit. In case of unequal delays, a race condition may cause the state variables to change in an unpredictable manner.
38. Define non critical race.
If the final stable state that the circuit reaches does not depend on the order in which the state variable changes, the race condition is not harmful and it is called a non critical race.
39. Define critical race?
If the final stable state depends on the order in which the state variable changes, the race condition is harmful and it is called a critical race.
40. What is a cycle?
A cycle occurs when an asynchronous circuit makes a transition through a series of unstable states. If a cycle does not contain a stable state, the circuit will go from one unstable to stable to another, until the inputs are changed.
41. List the different techniques used for state assignment.
1. Shared row state assignment
2. One hot state assignment.
42. Write a short note on fundamental mode asynchronous circuit.
Fundamental mode circuit assumes that. The input variables change only when the circuit is stable. Only one input variable can change at a given time and inputs are levels and not pulses.
43. Write a short note on pulse mode circuit.
Pulse mode circuit assumes that the input variables are pulses instead of level. The width of the pulses is long enough for the circuit to respond to the input and the pulse width must not be so long that it is still present after the new state is reached.
44. Define secondary variables
The delay elements provide a short term memory for the sequential circuit. The present state and next state variables in asynchronous sequential circuits are called secondary variables.
45. Define flow table in asynchronous sequential circuit.
In asynchronous sequential circuit state table is known as flow table because of the behaviour of the asynchronous sequential circuit. The stage changes occur in independent of a clock, based on the logic propagation delay, and cause the states to .flow. from one to another.
46. What is fundamental mode.
A transition from one stable state to another occurs only in response to a change in the input state. After a change in one input has occurred, no other change in any input occurs until the circuit enters a stable state. Such a mode of operation is referred to as a fundamental mode.
47. Write short note on shared row state assignment.
Races can be avoided by making a proper binary assignment to the state variables. Here, the state variables are assigned with binary numbers in such a way that only one state variable can change at any one state variable can change at any one time when a state transition occurs. To accomplish this, it is necessary that states between which transitions occur be given adjacent assignments. Two binary are said to be adjacent if they differ in only one variable.
48. Write short note on one hot state assignment.
The one hot state assignment is another method for finding a race free state
assignment. In this method, only one variable is active or hot for each row in the original flow table, ie, it requires one state variable for each row of the flow table. Additional row are introduced to provide single variable changes between internal state transitions.
PART  B (16 MARKS)
1. What is the objective of state assignment in asynchronous circuit? Give hazard – freerealization for the following Boolean function f(A,B,C,D) = _M(0,2,6,7,8,10,12)
2. Summarize the design procedure for asynchronous sequential circuit
a. Discuss on Hazards and races
b. What do you know on hardware descriptive languages?
3. Design an asynchronous sequential circuit with 2 inputs X and Y and with one output ZWherever Y is
1, input X is transferred to Z .When Y is 0; the output does not change forany change in X.Use SR
latch for implementation of the circuit
4. Develop the state diagram and primitive flow table for a logic system that has 2 inputs,xand y and an output z.And reduce primitive flow table. The behavior of the circuit is statedas follows. Initially x=y=0. Whenever x=1 and y = 0 then z=1, whenever x = 0 and y = 1then z = 0.When x=y=0 or x=y=1 no change in z ot remains in the previous state. Thelogic system has edge triggered inputs with out having a clock .the logic system changesstate on the rising edges of the 2 inputs. Static input values are not to have any effect inchanging the Z output
5. Design an asynchronous sequential circuit with two inputs X and Y and with one output Z.Whenever Y
is 1, input X is transferred to Z.When Y is 0,the output does not change forany change in X.
6. Obtain the primitive flow table for an asynchronous circuit that has two inputs x,y and oneoutput Z. An output z =1 is to occur only during the input state xy = 01 and then if the only ifthe input state xy =01 is preceded by the input sequence.
7. A pulse mode asynchronous machine has two inputs. It produces an output whenever twoconsecutive
pulses occur on one input line only .The output remains at ‘1’ until a pulse hasoccurred on the other
input line. Draw the state table for the machine.
8.(a) How will you minimize the number of rows in the primitive state table of an incompletelyspecified sequential machine
(b) State the restrictions on the pulse width in a pulse mode asynchronous sequentialmachine
9. Construct the state diagram and primitive flow table for an asynchronous network that hastwo inputs and one output. The input sequence X1X2 = 00,01,11 causes the output tobecome 1.The next input
change then causes the output to return to 0.No other inputs willproduce a 1 output
10. What are called as essential hazards? How does the hazard occur insequential circuits? How can the same be eliminated using SR latches?Give an example.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SUBJECT CODE: EC2203
DIGITAL ELECTRONICS (FOR THIRD SEMESTER ECE) PART B QUESTIONS WITH KEYS
1) Simplify the boolean function using tabulation method. F = m (0, 1, 2, 8, 10, 11, 14, 15)
Ã˜ List all the min terms
Ã˜ Arrange them as per the number of ones based on binary equivalent
Ã˜ Compare one group with another for difference in one and replace the bit with dash.
Ã˜ Continue this until no further grouping possible.
Ã˜ The unchecked terms represent the prime implicants.
Ã˜ F = W'X'Y' + X'Z' + WY
2) Determine the prime implicants of the function
F (W,X,Y,Z) = _ (1,4,6,7,8,9,10,11,15)
Ã˜ List all the min terms
Ã˜ Arrange them as per the number of ones based on binary equivalent
Ã˜ Compare one group with another for difference in one and replace the bit with dash.
Ã˜ Continue this until no further grouping possible.
Ã˜ The unchecked terms represent the prime implicants.
Ã˜ F = X'Y'Z + W'XZ' + W'XY + XYZ + WYZ + WX'
Ã˜ Minimum Set of prime implicants F = X'Y'Z + W'XZ' + XYZ + WX'
3) Simplify the Boolean function using Kmap. F(A,B,C,D,E) = (0,2,4,6,9,13,21,23,25,29,31)
Ã˜ Five variables hence two variable k maps one for A = 0 and the other for A = 1.
Ã˜ F = A'B'E' + BD'E + ACE
4) Obtain the canonical sum of products of the function Y = AB + ACD
Ã˜ Y = AB (C + C')(D + D') + ACD (B + B')
Ã˜ Y = ABCD + ABCD' + ABC'D + ABC'D' + AB'CD
5) State the postulates and theorems of Boolean algebra.
X + 0 = X X · 1 = X
X + X' = 1 X · X' = 0
X + X = XX · X = X X + 1 = 1 X · 0 = 0 (X')' = X
X + Y = Y + XXY = YX
X + (Y + Z) = (X + Y) + ZX(YZ) = (XY)Z
X(Y + Z) = XY + XZX + YX = (X + Y) (X + Z)
(X + Y)' = X'Y' (XY)' = X' + Y'
X + XY = X X(X + Y) = X
6. Explain with neat diagrams TTL.
Ã˜ Disadvantages of other families
Ã˜ Diagram of TTL
Ã˜ Theory
Ã˜ Working principle
7. Discuss all the characteristics of digital IC’s.
Ã˜ Fan out
Ã˜ Power dissipation
Ã˜ Propagation Delay
Ã˜ Noise Margin
Ã˜ Fan In
Ã˜ Operating temperature
Ã˜ Power supply requirements
8. Explain with neat diagram how an open collector TTL operates.
Ã˜ Disadvantages of other families
Ã˜ Diagram of open collector gate TTL
Ã˜ Theory
Ã˜ Working principle
9. Explain the different applications of open collector TTL.
Ã˜ Wired logic
Ã˜ Common bus system
Ã˜ Drive a lamp or relay
10. Explain in detail about schottky TTL.
Ã˜ Disadvantages of other families
Ã˜ Diagram of schottky TTL
Ã˜ Theory
Ã˜ Working principle
Ã˜ Advantages
11. Explain in detail about three state gate.
Ã˜ Disadvantages of other families
Ã˜ Explanation about three state gate
Ã˜ Theory
Ã˜ Working principle
12. Explain with necessary diagrams MOS & CMOS.
Ã˜ PMOS
Ã˜ NMOS
Ã˜ CMOS
Ã˜ Diagrams
Ã˜ 13.Design a 4bit binary adder/subtractor circuit.
Ã˜ Basic equations
Ã˜ Comparison of equations
Ã˜ Design using twos complement
Ã˜ Circuit diagram
14. Explain the working of BCD Ripple Counter with the help of state diagram and logicdiagram.
Ã˜ BCD Ripple Counter Count sequence
Ã˜ Truth Table
Ã˜ State diagram representing the Truth Table
Ã˜ Truth Table for the JK Flip Flop
Ã˜ Logic Diagram
15. Design a logic circuit to convert the BCD code to Excess – 3 code.
Ã˜ Truth Table for BCD to Excess – 3 conversion.
Ã˜ Kmap simplification
Ã˜ Logic circuit implementing the Boolean Expression
16. Design and explain a comparator to compare two identical words.
Ã˜ Two numbers represented by A = A3A2A1A0 & B = B3B2B1B0
Ã˜ If two numbers equal P = Ai .Bi
Ã˜ Obtain the logic Expression.
Ã˜ Obtain the logic diagram.
17. Design a sequential detector which produces an output 1 every time the input sequence
Ã˜ 1011 is detected.
Ã˜ Construct state diagram
Ã˜ Obtain the flow table
Ã˜ Obtain the flow table & output table
Ã˜ Transition table
Ã˜ Select flip flop
Ã˜ Excitation table
Ã˜ Logic diagram
18. Explain in detail about serial in serial out shift register.
Ã˜ Block diagram
Ã˜ Theoretical explanation
Ã˜ Logic diagram
Ã˜ Working
19.Explain with neat diagram the different hazards and the way to eliminate them.
Ã˜ Classification of hazards
Ã˜ Static hazard & Dynamic hazard definitions
Ã˜ K map for selected functions
Ã˜ Method of elimination
Ã˜ Essential hazards
20.State with a neat example the method for the minimization of primitive flow table.
Ã˜ Consider a state diagram
Ã˜ Obtain the flow table
Ã˜ Using implication table reduce the flow table
Ã˜ Using merger graph obtain maximal compatibles
Ã˜ Verify closed & covered conditions
Ã˜ Plot the reduced flow table
21.Design a asynchronous sequential circuit with 2 inputs T and C. The output attains a value of 1 when T = 1 & c moves from 1 to 0. Otherwise the output is 0.
Ã˜ Obtain the state diagram
Ã˜ Obtain the flow table
Ã˜ Using implication table reduce the flow table
Ã˜ Using merger graph obtain maximal compatibles
Ã˜ Verify closed & covered conditions
Ã˜ Plot the reduced flow table
Ã˜ Obtain transition table
Ã˜ Excitation table
Ã˜ Logic diagram
22. Explain in detail about Races.
Ã˜ Basics of races
Ã˜ Problem created due to races
Ã˜ Classification of races
Ã˜ Ready for races cycles
23. Explain the different methods of state assignment
Ã˜ Three row state assignment
Ã˜ Shared row state assignment
Ã˜ Four row flow table
Ã˜ Multiple row state assignment
Ã˜ Prevention of races.
24. Explain in detail about PLA with a specific example.
Ã˜ Explanation about ROM
Ã˜ Classifications of ROM
Ã˜ Architecture of ROM
Ã˜ Specification of PLA
Ã˜ Specific Example
Ã˜ Related Diagram
Ã˜ Related Table.
25. Implement the following using a mux. F(a,b,c,d) = _(0,1,3,4,8,9,15)
Ã˜ Obtain the truth table
Ã˜ From the truth table realize the expressions for the outputs and inputs
Ã˜ Realize the logic diagram.
26.Explain with neat diagrams a RAM architecture.
Ã˜ Different Memories
Ã˜ Classification of memories
Ã˜ RAM architecture diagram
Ã˜ Timing waveforms
Ã˜ Coincident Decoding
Ã˜ Read write operations
27.Explain in detail about PLA and PAL.
Ã˜ Basic ROM
Ã˜ Classification of PROM
Ã˜ Logic difference between Prom & PLA
Ã˜ Logic diagram implementing a function
Ã˜ Logic difference between Prom & PAL
Ã˜ Logic diagram implementing a function
28.Explain with neat diagrams a ROM architecture.
Ã˜ Different Memories
Ã˜ Classification of memories
Ã˜ ROM architecture diagram
Ã˜ Timing waveforms
Ã˜ Coincident Decoding
Ã˜ Read write operations
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