Digital Logic Circuits - Design and Analysis of Counters

Design of Counters

A sequential circuit that goes through a prescribed sequence of states upon the application of input pulses is called a counter. The input pulses, called count pulses, may be clock pulses. In a counter, the sequence of states may follow a binary count or any other sequence of states. Counters are found in almost all equipment containing digital logic. They are used for counting the number of occurrences of an even and are useful for generating timing sequences to control operations in a digital system.

Of the various sequences a counter may follow, the straight binary sequence is the simplest and most straight forward. A counter that follows the binary sequence is called a binary counter. An n-bit binary counter consists of n flip-flops and can count in binary from 0 to 2n - 1.

Design of Counters

This example is taken from T. L. Floyd, Digital Fundamentals, Fourth Edition, Macmillan Publishing, 1990, p.395.

Example 1.5   A counter is first described by a state diagram, which is shows the sequence of states through which the counter advances when it is clocked. Figure 18 shows a state diagram of a 3-bit binary counter.

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Figure 18. State diagram of a 3-bit binary counter.

The circuit has no inputs other than the clock pulse and no outputs other than its internal state (outputs are taken off each flip-flop in the counter). The next state of the counter depends entirely on its present state, and the state transition occurs every time the clock pulse occurs. Figure 19 shows the sequences of count after each clock pulse.

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Fig.19 Count sequence after each pulse

Once the sequential circuit is defined by the state diagram, the next step is to obtain the next-state table, which is derived from the state diagram in Figure 18 and is shown in Table 15.

Table 15. State table

Present State

Q2 Q1 Q0

Next State

Q2 Q1 Q0

0   0   0

0   0   1

0   1   0

0   1   1

1   0   0

1   0   1

1   1   0

1   1   1

0   0   1

0   1   0

0   1   1

1   0   0

1   0   1

1   1   0

1   1   1

0   0   0

Since there are eight states, the number of flip-flops required would be three. Now we want to implement the counter design using JK flip-flops.

Next step is to develop an excitation table from the state table, which is shown in Table 16.

Table 16. Excitation table

Output State Transitions

Flip-flop inputs

J2 K2

J1 K1

J0 K0

Present State

Q2 Q1 Q0

Next State

Q2 Q1 Q0

0  0  0

0  0  1

0  1  0

0  1  1

1  0  0

1  0  1

1  1  0

1  1  1

0  0  1

0  1  0

0  1  1

1  0  0

1  0  1

1  1  0

1  1  1

0  0  0

0 X

0 X

1 X

0 X

1 X

X 1

0 X

X 0

1 X

1 X

X 1

X 1

X 0

0 X

1 X

X 0

1 X

X 1

X 0

X 0

1 X

X 1

X 1

X 1

Now transfer the JK states of the flip-flop inputs from the excitation table to Karnaugh maps to derive a simplified Boolean expression for each flip-flop input. This is shown in Figure 20.

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Figure 20. Karnaugh maps

The 1s in the Karnaugh maps of Figure 20 are grouped with "don't cares" and the following expressions for the J and K inputs of each flip-flop are obtained:

     J0 = K0 = 1

     J1 = K1 = Q0

     J2 = K2 = Q1*Q0

The final step is to implement the combinational logic from the equations and connect the flip-flops to form the sequential circuit. The complete logic of a 3-bit binary counter is shown in Figure 21.

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Figure 21. Logic diagram of a 3-bit binary counter

Design of Counters

This example is taken from M. M. Mano, Digital Design, Prentice Hall, 1984, p.243.

Example 1.6     Design a counter specified by the state diagram in Example 1.5 using T flip-flops. The state diagram is shown here again in Figure 22.

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Figure 22. State diagram of a 3-bit binary counter.

The state table will be the same as in Example 1.5.

Now derive the excitation table from the state table, which is shown in Table 17.

Table 17. Excitation table.

Output State Transitions

Flip-flop inputs

T2  T1  T0

Present State

Q2 Q1 Q0

Next State

Q2 Q1 Q0

0   0   0

0   0   1

0   1   0

0   1   1

1   0   0

1   0   1

1   1   0

1   1   1

0   0   1

0   1   0

0   1   1

1   0   0

1   0   1

1   1   0

1   1   1

0   0   0

0    0    1

0    1    1

0    0    1

1    1    1

0    0    1

0    1    1

0    0    1

1    1    1

Next step is to transfer the flip-flop input functions to Karnaugh maps to derive a simplified Boolean expressions, which is shown in Figure 23.

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Figure 23. Karnaugh maps

The following expressions are obtained:

T0 = 1;        T1 = Q0;         T2 = Q1*Q0

Finally, draw the logic diagram of the circuit from the expressions obtained. The complete logic diagram of the counter is shown in Figure 24.

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Figure 24. Logic diagram of 3-bit binary counter.

Now that you have reached the end of the tutorial, you should be able to understand the basic concept of sequential circuits. You should be able to analyse and design a basic sequential circuit. Now you can practice some of the exercises using the analysis and design procedures shown in the examples.

Exercises

You can try some of these exercises which covers the analysis and design of sequential circuits.

Analysis of Sequential Circuits.

1.    Derive a) excitation equations, b) next state equations, c) a state/output table, and d) a state diagram for the circuit shown in Figure 1.1. Draw the timing diagram of the circuit.

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Figure 1.1

2.    Derive a) excitation equations, b) next state equations, c) a state/output table, and d) a state diagram for the circuit shown in Figure 1.2.

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Figure 1.2

3.    Derive a) excitation equations, b) next state equations, c) a state/output table, and d) a state diagram for the circuit shown in Figure 1.3.

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Figure 1.3

4.    Derive the state output and state diagran for the sequential circuit shown in Figure 1.4.

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Figure 1.4

5.    A sequential circuit uses two D flip-flops as memory elements. The behaviour of the circuit is described by the following equations:

     D1 = Q1 + x'*Q2

     D2 = x*Q1' + x'*Q2

       Z = x'*Q1*Q2 + x*Q1'*Q2'

Derive the state table and draw the state diagram of the circuit.

Design of Sequential Circuits.

6.    Design a sequential circuit specified by Table 6.1, using JK flip-flops.

Table 6.1

          Present State

Q0 Q1

       Next State

x = 0

x = 1

     Output

x = 0

x = 1

0 0

0 1

1 0

1 1

0 0

0 1

0 0

1 0

1 1

1 0

0 0

0 1

0

0

0

0

0

0

0

1

7.    Design the sequential circuit in question 6, using T flip-flops.

8.    Design a mod-5 counter which has the following binary sequence: 0, 1, 2, 3, 4. Use JK flip-flops.

9.    Design a counter that has the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6, 7. Use RS flip-flops.

10.  Design a counter with the following binary sequence: 1, 2, 5, 7 and repeat. Use JK flip-flops.

11.  Design a counter with the following repeated binary sequence: 0, 4, 2, 1, 6. Use T flip-flops.

12.  Design a counter that counts in the sequence 0, 1, 3, 6, 10, 15, using four a) D, b) SR, c) JK and d) T flip-flops.