Digital Logic Circuits - FPGA Structural Classification

FPGA Structural Classification

Programmble Logic Devices

There is a constant effort on the part of system designers to design systems with improved performance, efficiency and flexibility.

Today, if one wants to make effective and competitive use of these general purpose blocks, then one of the better ways is to use reconfigurable hardware that allows user programmability.

The first form of reconfigurable device was Programmable Logic Devices which consisted of arrays of AND and OR gates with programmable metal paths as interconnection between them. They could be programmed to into a single chip to meet specific requirements. PLDs later evolved into what was later known as FPGAs.

Basic structure of an FPGA includes logic elements, programmable interconnects and memory. Arrangement of these blocks is specific to particular manufacturer. On the basis of internal arrangement of blocks FPGAs can be divided into three classes:

Symmetrical arrays

This architecture consists of logic elements(called CLBs) arranged in rows and columns of a matrix and interconnect laid out between them. This symmetical matrix is surrounded by I/O blocks which connect it to outside world. Each CLB consists of n-input Lookup table and a pair of programmable flip flops. I/O blocks also control functions such as tri-state control, output transition speed. Interconnects provide routing path. Direct interconnects between adjacent logic elements have smaller delay compared to general purpose interconnet.


Row based architecture

Row based architecture consists of alternating rows of logic modules and programmable interconnect tracks. Input output blocks are located in the periphery of the rows. One row may be connected to adjacent rows via vertical interconnect. Logic modules can be implemented in various combinations. Combinatorial modules contain only combinational elements which Sequential modules contain both combinational elements along with flip flops. This sequential modules can implement complex combinatorial-sequential functions. Routing tracks are divided into smaller segments connected by anti-fuse elements between them.


Hierarchical PLDs

This architecture is designed in hierarchical manner with top level containing only logic blocks and interconnects. Each logic block contains number of logic modules. And each logic module has combinatorial as well as sequential functional elements. Each of these functional elements is controlled by the programmed memory. Communication between logic blocks is achieved by programmable interconnect arrays. Input output blocks surround this scheme of logic blocks and interconnects.


Programming Methodology

Electrically programmable switches are used to program an FPGA. Performance of an FPGA in terms of area and logic density is a function of properties of these switches.

Properties of these programmable switches that make difference are on-resistance, parasitic capacitance, volatility, re-programmability, size etc.

Various approaches to provide user programmability are :

SRAM programming technology

Static RAM cells are used to control pass gates or multiplexers. To use pass gate as closed switch, boolean one is stored in SRAM cell. When zero is stored pass transistor provides high resistance between two wire segments. Figure a depicts this usage of SRAM.


To use SRAM as multiplexer, state of control values stored in SRAM decides which of the multiplexer inputs are connected to the output as shown in figure b.

Advantage of SRAM is that it provides fast re-programmability and integrated circuit fabrication technology is required to build it. While disadvantage is the space it consumes as minimum five transistors are required to implement a memory cell.

Floating Gate Programming

Technology found in ultaviolet erasable EPROM and electrically erasable EEPROM devices is used in FPGA from Altera. The programmable switch is a transistor that permanently be disabled.

Here again the advantage is reprogrammability but there is another advantage no external permanent memory source is need to program it at power-up. However it requires three additional processing steps over CMOS technology. Other disadvantages are high static power consumption due to pull up resistor and high ON-resistance of EPROM transistor.


Electrically programmable EPROM is used by AMD and Lattice. Use of EEPROM gives advantage of easy reprogrammability. However EEPROM cell is twice as large as EPROM cell.

Antifuse programming methodology

An Antifuse is a two terminal device with an unprogrammed state providing very high resistance between its terminals. To create a low resistance link between the two terminals high voltage is applied accross the terminals to blow the antifuse. Extra bit of circuitry is required to program an antifuse. Antifuse technology is used by FPGA's from Actel, QuickLogic and Crosspoint.

Advantage of Antifuse is relatively small size and hence area reduction which is anulled by area consumed by extra circuitry to program it. Another big advantage is low series resistance and low parasitic capacitance.

FPGA Design Flow

One of the most important advantages of FPGA based design is that users can design it using CAD tools provided by design automation companies.

Generic design flow of an FPGA includes following steps:

System Design

At this stage designer has to decide what portion of his functionality has to be implemented on FPGA and how to integrate that functionality with rest of the system.

I/O integration with rest of the system

Input Output streams of the FPGA are integrated with rest of the Printed Circuit Board, which allows the design of the PCB early in design process. FPGA vendors provide extra automation software solutions for I/O design process.

Design Description

Designer describes design functionality either by using schema editors or by using one of the various Hardware Description Languages(HDLs) like Verilog or VHDL.


Once design has been defined CAD tools are used to implement the design on a given FPGA. Synthesis includes generic optimization, slack optimizations, power optimizations followed by placement and routing. Implementation includes Partition, Place and route. The output of design implementation phase is bit-stream file.

Design Verification

Bit stream file is fed to a simulator which simulates the design functionality and reports errors in desired behavior of the design. Timing tools are used to determine maximum clock frequency of the design. Now the design is loading onto the target FPGA device and testing is done in real environment.

Example :

Below given circuit consists of gates and flip flops. Combinational elements of the circuit are covered by a 4-input Look up table(4-LUT). Sequential elements in the input circuit map to flip flops on the FPGA. Placement of these elements is done in such a way as to minimize wiring during routing.