Digital Logic Circuits - Design of Sequential Circuits

Design of Sequential Circuits

This example is taken from M. M. Mano, Digital Design, Prentice Hall, 1984, p.235.

Example 1.3 We wish to design a synchronous sequential circuit whose state diagram is shown in Figure 13. The type of flip-flop to be use is J-K.

Figure 13. State diagram

From the state diagram, we can generate the state table shown in Table 9. Note that there is no output section for this circuit. Two flip-flops are needed to represent the four states and are designated Q0Q1. The input variable is labelled x.

Table 9. State table.

Present State Q0 Q1	Next State x = 0 x = 1
0 0 0 1 1 0 1 1	0 0 0 1 1 0 0 1 1 0 1 1 1 1 0 0

We shall now derive the excitation table and the combinational structure. The table is now arranged in a different form shown in Table 11, where the present state and input variables are arranged in the form of a truth table. Remember, the excitable for the JK flip-flop was derive in

Table 10. Excitation table for JK flip-flop

Output Transitions Q Q(next)	Flip-flop inputs J K
0      0 0      1 1      0 1      1	0  X 1  X X  1 X  0

Table 11. Excitation table of the circuit

Present State Q0 Q1	Next State Q0 Q1	Input x	Flip-flop Inputs J0 K0 J1 K1
0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1	0 0 0 1 1 0 0 1 1 0 1 1 1 1 0 0	0 1 0 1 0 1 0 1	0 X 0 X 0 X 1 X 1 X X 1 0 X X 0 X 0 0 X X 0 1 X X 0 X 0 X 1 X 1

In the first row of Table 11, we have a transition for flip-flop Q0 from 0 in the present state to 0 in the next state. In Table 10 we find that a transition of states from 0 to 0 requires that input J = 0 and input K = X. So 0 and X are copied in the first row under J0 and K0 respectively. Since the first row also shows a transition for the flip-flop Q1 from 0 in the present state to 0 in the next state, 0 and X are copied in the first row under J1 and K1. This process is continued for each row of the table and for each flip-flop, with the input conditions as specified in Table 10.

The simplified Boolean functions for the combinational circuit can now be derived. The input variables are Q0, Q1, and x; the output are the variables J0, K0, J1 and K1. The information from the truth table is plotted on the Karnaugh maps shown in Figure 14.

Figure 14. Karnaugh Maps

The flip-flop input functions are derived:

J0 = Q1*x'        K0 = Q1*x

J1 = x                K1 = Q0'*x' + Q0*x = Q0x

Note: the symbol  is exclusive-NOR.

The logic diagram is drawn in Figure 15.

Figure 15. Logic diagram of the sequential circuit.

Design of Sequential Circuits

This example is taken from P. K. Lala, Practical Digital Logic Design and Testing, Prentice Hall, 1996, p.176.

Example 1.4     Design a sequential circuit whose state tables are specified in Table 12, using D flip-flops.

Table 12. State table of a sequential circuit.

Present State Q0 Q1	Next State x = 0 x = 1	Output x = 0 x = 1
0 0 0 1 1 0 1 1	0 0 0 1 0 0 1 0 1 1 1 0 0 0 0 1	0 0 0 0 0 0 0 1

Table 13. Excitation table for a D flip-flop.

Output Transitions QQ(next)	Flip-flop inputs D
0      0 0      1 1      0 1      1	0 1 0 1

Next step is to derive the excitation table for the design circuit, which is shown in Table 14. The output of the circuit is labelled Z.

Table 14. Excitation table

Present State Q0 Q1	Next State Q0 Q1	Input x	Flip-flop Inputs D0 D1	Output Z
0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1	0 0 0 1 0 0 1 0 1 1 1 0 0 0 0 1	0 1 0 1 0 1 0 1	0 0 0 1 0 0 1 0 1 1 1 0 0 0 0 1	0 0 0 0 0 0 0 1

Now plot the flip-flop inputs and output functions on the Karnaugh map to derive the Boolean expressions, which is shown in Figure 16.

Figure 16. Karnaugh maps

The simplified Boolean expressions are:

D0 = Q0*Q1' + Q0'*Q1*x

D1 = Q0'*Q1'*x + Q0*Q1*x + Q0*Q1'*x'

Z = Q0*Q1*x

Finally, draw the logic diagram.

Figure 17. Logic diagram of the sequential circuit.