Design of Sequential Circuits
This example is taken from M. M. Mano, Digital Design, Prentice Hall, 1984, p.235.
Example 1.3 We wish to design a synchronous sequential circuit whose state diagram is shown in Figure 13. The type of flipflop to be use is JK.
Figure 13. State diagram
From the state diagram, we can generate the state table shown in Table 9. Note that there is no output section for this circuit. Two flipflops are needed to represent the four states and are designated Q0Q1. The input variable is labelled x.
Table 9. State table.
Present State
 Next State
 


We shall now derive the excitation table and the combinational structure. The table is now arranged in a different form shown in Table 11, where the present state and input variables are arranged in the form of a truth table. Remember, the excitable for the JK flipflop was derive in
Table 10. Excitation table for JK flipflop
Output Transitions
 Flipflop inputs
 


Table 11. Excitation table of the circuit
Present State
 Next State
 Input
 Flipflop Inputs
 




In the first row of Table 11, we have a transition for flipflop Q0 from 0 in the present state to 0 in the next state. In Table 10 we find that a transition of states from 0 to 0 requires that input J = 0 and input K = X. So 0 and X are copied in the first row under J0 and K0 respectively. Since the first row also shows a transition for the flipflop Q1 from 0 in the present state to 0 in the next state, 0 and X are copied in the first row under J1 and K1. This process is continued for each row of the table and for each flipflop, with the input conditions as specified in Table 10.
The simplified Boolean functions for the combinational circuit can now be derived. The input variables are Q0, Q1, and x; the output are the variables J0, K0, J1 and K1. The information from the truth table is plotted on the Karnaugh maps shown in Figure 14.
Figure 14. Karnaugh Maps
The flipflop input functions are derived:
J0 = Q1*x' K0 = Q1*x 
J1 = x K1 = Q0'*x' + Q0*x = Q0x 
Note: the symbol is exclusiveNOR.
The logic diagram is drawn in Figure 15.
Figure 15. Logic diagram of the sequential circuit.
Design of Sequential Circuits
This example is taken from P. K. Lala, Practical Digital Logic Design and Testing, Prentice Hall, 1996, p.176.
Example 1.4 Design a sequential circuit whose state tables are specified in Table 12, using D flipflops.
Table 12. State table of a sequential circuit.
Present State
 Next State
 Output
 



Table 13. Excitation table for a D flipflop.
Output Transitions
 Flipflop inputs
 


Next step is to derive the excitation table for the design circuit, which is shown in Table 14. The output of the circuit is labelled Z.
Table 14. Excitation table
Present State
 Next State
 Input
 Flipflop Inputs
 Output
 





Now plot the flipflop inputs and output functions on the Karnaugh map to derive the Boolean expressions, which is shown in Figure 16.
Figure 16. Karnaugh maps
The simplified Boolean expressions are:
D0 = Q0*Q1' + Q0'*Q1*x 
D1 = Q0'*Q1'*x + Q0*Q1*x + Q0*Q1'*x' 
Z = Q0*Q1*x 
Finally, draw the logic diagram.
Figure 17. Logic diagram of the sequential circuit.
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